Low power CMOS NAND gate using DVS and mutithreshold CMOS technique

In digital and analog circuits, power consumption plays an important role in CMOS device. Due to scale down technology in VLSI circuits the threshold voltage of transistors reduced but increases in subthreshold leakage current. To reduce the subthreshold leakage current the effective circuit level technique is proposed. In this paper, the MTCMOS technique is proposed which gives high speed and low power dissipation by maintaining the performance of the circuits. The NAND gate is designed using DVS and MTCMOS technique gives least power consumption. All the simulations have been performed on Tanner EDA Tool version 14.1. The proposed technique reduces the power dissipation by 30% to 70%.