Thermal design and analysis of through silicon interposer (TSI) package

Through Silicon Interposer (TSI) technology is one of the most promising platforms for the next generation packages, due to its low power and high interconnect bandwidth in the package design. TSI is built on top of COC (chip on chip) and engaged with the connection to the external world, which allows I/O pitches less than 50um. Moreover, with BEOL (Back-End-of-Line) Cu Damascene technology, fine pitch chip-to-chip routing is achievable (Line width/Line spacing 0.4um/0.4um). In order to achieve high power requirements or better thermal performance, thermal design and analysis should be considered. Together with SI (signal integration) and PI (power integration) in chip level and package level, board level design has more freedom to introduce cooling component in the package so that to dissipate the extra heat, which can't be dissipated in chip and package level. EMC (epoxy molding compound) was proposed to be backgrinded to zero overmold to reduce the thermal resistance in package level. In the board level design, we mainly focus on the thermal design using heat sink. The air cooling system is chosen due to its simplicity and lower cost than other designs like liquid cooling. The material of aluminum is chosen for the proposed heat sink to reduce the total cost and weight of the heat sink. The heat sink is finally selected and its efficiency is carefully studied, comparing to the design data sheet. A total heat dissipation capability of 77.5 W is defined for the proposed DRAM and FPGA with localized heat source effect. Simulation methodology was built up by ANSYS icepak software with forced air cooling solution. TIM, FPGA, DRAM, micro bump layer, organic BT substrate, C4 ball layer and PCB board are all included in the design and simulation. The key to success lies on BLT control of the TIM layer.