Passive stress sensor development: From 65nm to 28nm technology nodes

This paper deals with the development and optimization of a passive stress sensor (PSS) with respect to 28nm node designing rules and compare its performances to a 65nm node previously developed in-house one. First, a finite element analysis (FEA) leads to the main design and dimensions of the PSS, then, once embedded in a microchip, the gauge factors have been calibrated using four-point bending (FPB) method so as to verify the numerical assumptions. This sensor may be used in various applications and particularly in flip chip (FC) assembly in which stress within low-k layers needs to be limited. Finally, and in order to illustrate the sensor ability (dimensions and sensitivity), a typical FC assembly is simulated and discussed.