Novel LC resonant clocking for 3D IC using TSV-inductor and capacitor

At sub-14nm regime, large area overhead induced by on-chip capacitor and inductor is a major concern to ensure power integrity or enable on-chip applications. To overcome this issue, a novel 3D Through-Silicon-Via (TSV) based capacitor is investigated in this work, which may achieve both high density and high performance. The capacitor simulated in this work alleviates the depletion effect adding doping region around the TSV so that the capacitor can maintain its maximum value within operation voltage range. Moreover, the equivalent serial resistance of the proposed capacitor is reduced through doping and distributed grounded contact technology. An LC resonant clock is also simulated in this work, by replacing conventional capacitor and inductor to TSV based structures, it may achieve a 16.3x capacitor area reduction and 2.2x inductor area reduction while the performance stays almost the same.