Investigation of the capacitance compensation structure for wire-bonding interconnection in multi-chips module

In this paper, a capacitance compensation structure for wire-bonding interconnection in multi-chips module is investigated. The equivalent circuit model is built to analyze the characteristics of the wire-bonding interconnection. Furthermore, the relationships between the structure parameters and the transmission behaviors of the bonding wire are discussed. In order to meet the impedance matching of the wire-bonding at high frequency, a capacitance compensation structure is presented. In comparison with the uncompensated structure, the parasitic effects of the bonding wire is minimized and the return loss is increased about 20 dB with the proposed design.