An analysis technique for improving delay factor of carry select adder using FPGA

This paper introduces Field Programmable Gate Array (FPGA) model of modified Carry Select Adder (CSLA) for enhancing conventional CSLA speed based on its performance analysis. The delay factor has been improved by using other adders' blocks and common logic blocks instead of Ripple Carry Adder (RCA) blocks used in conventional CSLA. Modifying CSLA architecture at a fundamental level is an advantageous concept that sets FPGA based adder models apart from rigid-architecture conventional adders. This paper introduces also design and synthesis of one-level and two-level modified CSLA and the obtained results show some improvements in the time delay (T) by about 44.7% and in the area (A) by about 15.1% in comparison with conventional CSLA performance. It is also shown that the two-level modified CSLA with Brent-Kung Adder (BKA) introduces some significant improvement in the performance in terms of AT and AT
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