Silicon on metal technology merged with cylindrical gate all around FET for enhanced performance

Buried oxide layer in SOI devices creates a few problems such as self-heating, which eventually flops the possibility of this device for future circuit analysis. A modification over a fully depleted SOI MOSFET merged with cylindrical gate all around (CGAA) structure is proposed in this work to incorporate improved performance along with a possibility to dissipate the heat generated in the device. The buried oxide layer is replaced with thin P
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region and the substrate layer is replaced by a metallic nanowire which is located at the center of the GAA core. The metallic nanowire is shorted with the gate metal to give in strong govern over the flow of the current and helps the device to release its heat easily. This modified structure is termed as silicon on metal (SOM) CGAA FET and was simulated using SILVACO TCAD ATLAS for short technology nodes. To exhibit the superiority of the device the simulation results were compared with CGAA FET. The device shows an improved electrical characteristics and scaling possibility below 10nm technology node over CGAA FET which makes this modified device potentially suitable for future CMOS technology.