Design of a 1.8V-input 6.5V-output digital level shifter for trimming application

A 1.8V input, 6.5V output step-up digital level shifter is proposed. It is based on contention mitigated digital level shifter (CMLS) but it uses single supply only instead of two. It uses a complete, stand-alone, and unregulated voltage charge pump circuit that generates a 6.5V output voltage from a 1.8V input. Charge pump output is then used as high-side supply (VDDH) of the step-up level shifter, while the low-side supply (VDD
_l
) is externally-supplied 1.8V. Compared to the conventional level shifter where two separate supply voltages (VDD
_l
and VDD
_H
) are required, the proposed design uses a single supply to shifted-up a digital signals. This technique simplifies the user-end power supply requirement of the system, thus the proposed level shifter design is applicable in many low-power and power-constraint applications such as in mobile and portable devices application. The proposed design is implemented using 0.35-μm TSMC CMOS technology. The schematic and the nestlist have been designed and extracted using LTSPICE tool; while the simulation has been carried out using the HSPICE circuit simulator.