First vertically stacked GeSn nanowire pGAAFETs with Ion = 1850μA/μm (Vov = Vds = −1V) on Si by GeSn/Ge CVD epitaxial growth and optimum selective etching

High material quality of compressively strained GeSn quantum wells sandwiched by Ge barriers on 200mm SOI wafers by CVD are confirmed by reciprocal space mapping (RSM), X-ray diffraction (XRD), and photoluminescence (PL). Due to the growth of relaxed Ge buffer on SOI, the misfit dislocations are confined near the Ge buffer/SOI interface, yielding low defect densities in the stacked GeSn channels. The low selectivity of Cl
₂
/HBr between GeSn and Ge, makes it impossible to perform the channel release for stacked devices by etching away the Ge barriers. The channel release by optimum H
₂
O
₂
etching for stacked two GeSn nanowires with [Sn] = 6%, hole concentration = 1.3E19cm
^-3
, and channel length (L
_CH
) = 150nm yields I
_on
per channel width = 1400μA/μm for junctionless (JL) devices. Further improvement of Ion to reach record value of I
_on
= 1850 p.A/p.m is achieved by increasing [Sn] to 10%, hole concentration to 6.7E19cm
^-3
and reducing the L
_CH
to 60nm. Additional 6.3% enhancement of I
_on
is obtained by additional uniaxial compressive strain using wafer bending. The best SS values of 84mV/dec and 88mV/dec are obtained for single-wire and stacked two-wire channels, respectively. JL has lower low frequency (LF) noise than inversion mode (IM) due to its bulk conduction nature. The mobility of JL and IM is dominated by impurity scattering and phonon scattering, respectively, according to the temperature dependence.