New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability

In this paper, hot carrier degradation (HCD) in FinFET is studied for the first time from trap-based approach rather than conventional carrier-based approach, with full Vgs/Vds bias characterization and self-heating correction. New HCD time dependence is observed, which cannot be predicted by traditional models. A trap-based HCD compact model is proposed and verified in both n- and p-type FinFETs, which is unified across different Vgs/Vds regions with different carrier transport mechanisms. Impacts of HCD on analog circuits is also demonstrated, showing bias runaway effect. The results provide new insights of HCD in FinFET, which are helpful to circuit design for reliability.