3D system package architecture as alternative to 3D stacking of ICs with TSV at system level

The 3D packaging started in 1970s for packaging of memory packages. Memory density has always been the bottleneck in high performance computing systems that led to two paths; increasing memory density within a chip in 2D and increasing by stacking many either packaged or bare chips in 3D. The barrier to systems performance, however, has been latency and bandwidth between logic and memory. 3D stacking of logic and memory has been viewed as the ultimate solution for a decade but it has its own barriers. While these barrier are being overcome by many approaches, the ultimate goal is to form miniaturized systems with highest performance and reliability at lowest cost. This paper presents a 3D system package architecture to address both bandwidth and other system requirements at system level in contrast to 3D ICs at device level.