Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs

Latest SOC trends include multiple asynchronous clock domains, each covering large silicon areas. Clock-Stop & State-Dump (CSSD) is a commonly used silicon debug technique that relies on stopping clocks and reconfiguring flip-flops as one or more scan chains. This paper describes an architecture for stopping clocks deterministically to allow safe state preservation before reconfiguring a circuit. Conditions for determinism are defined and a design IP to implement CSSD is described. Considerations for supporting an IP-SOC design methodology are also specified. The design was implemented and validated in Xilinx' 16nm FPGA family.