Test Compression with Single-Input Data Spreader and Multiple Test Sessions

Test time and test data volume required to test modern integrated circuits grow rapidly with circuit complexity. Test compression is now widely used in industry to reduce test cost. In this paper, a simple yet highly efficient test data compression technique with small area overhead is presented. Efficient algorithms are developed to determine configurations of the test decompressor and corresponding test patterns in multiple test sessions. These algorithms result in higher test compression ratio and lower test application time with less CPU runtime compared to the latest previous work. Experimental results on IWLS'05 benchmark circuits show that on average we can increase the compression factor by 17.26%, decrease the test application time by 12.28% and cut down the CPU time by 42.92%, with only slight increase of area overhead. More importantly, up to 1500x test compression factor is achieved for a design containing about 2M gates, with only 0.1% area overhead.