A Low Phase Noise 210-GHz Triple-Push Ring Oscillator in 90-nm CMOS

In this paper, a 210-GHz triple-push voltage-controlled oscillator consisting of two antiparallel inductor-capacitor ring oscillators with shared inductors is presented. By properly designing the sizes of the ring oscillators and a symmetrical layout, the power of the third harmonic and its phase noise are optimized. A codesign of the inductors, the output combiner, and the pad provides a low-loss signal path at third harmonic and natural filtering at all other harmonics. A prototype of the proposed oscillator is implemented in a 90-nm standard CMOS process. The oscillator achieves a low phase noise of -88 dBc/Hz at 1-MHz offset and -111.5 dBc/Hz at 10-MHz offset with a peak output power of -6 dBm at 210 GHz. The resulting figure of merit is -179.7 dBc/Hz at 1-MHz offset and -183.4 dBc/Hz at 10-MHz offset. The oscillator consumes 28.6 mW of dc power from a 1.1-V supply voltage and occupies a compact area of 0.17 mm
²
due to the simplicity of the architecture. The oscillator covers a frequency range from 204.3 to 215 GHz.