Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

Negative capacitance field effect transistor (NCFET) is designed in 5-nm FinFET node, which simultaneously meets the low-power and high-performance targets of
${I}_{ \mathrm{\scriptscriptstyle ON}}$
and
${I}_{ \mathrm{\scriptscriptstyle OFF}}$
at
${V}_{\sf dd}= 0.5$
V and
${V}_{\sf dd}= 0.23$
V, respectively, while the international roadmap for devices and systems (ITRS 2.0) projected
${V}_{\sf dd}$
is 0.65 V for both. The impact of power supply and parasitic capacitance on the performance of NCFET is studied. It is demonstrated that NCFET can be designed for fluid subthreshold swing (SS) behavior such that SS is degraded around
${V}_{\sf gs}=0$
,
${V}_{\sf ds}={V}_{\sf dd}$
, and is improved in the subthreshold region. This helps in combating OFF-current variation due to the threshold voltage fluctuations. A compact model to determine such design conditions is presented. Parasitic capacitance and the ferroelectric material parameters should be cooptimized for the target
${V}_{\sf dd}$
.