Realizing virtual output queues in high throughput data center nodes

Contemporary Data Center designs involve optical switches and Top-of-Rack (ToR) switches to connect thousands of servers. Most often ToR switches include Virtual Output Queues (VOQs) to alleviate the effect of the head-of-line blocking problem and improve the network's performance. The design of the VOQs has to minimize the latency in frame transmission and to keep the implementation cost, which includes buffers and the organization overhead, at relatively low level. The current paper focuses on a data center operating with Time Division Multiple Access (TDMA) method and presents a VOQ architecture placed at the input of the ToR switch supporting 10GEthernet port. The VOQ architecture consists of a limited number of queues corresponding to the active destinations of each input port, which forward the Ethernet frames to a shared buffer. A low latency efficient mechanism assigns the active destinations to the queues. This work is part of a complete ToR design that is developed with a commercial Ethernet switch, a Xilinx Virtex VC707 and a Xilinx NetFPGA boards. The VOQs are realized and validated on the NetFPGA board.