Wirelength and memory optimized rectilinear steiner minimum tree routing

Rectilinear Steiner minimal tree (RSMT) construction is a fundamental issue in designing very large scale integrated Integration (VLSI). FLUTE (Fast Look-Up table) based approach presented a fast and accurate RSMT construction for both smaller and higher degree nets. The model reduces the time complexity for RSMT construction for smaller nets, however for larger nets there exists memory overhead. Since flute based model did not consider the memory requirement in constructing RSMT, the proposed work presents a memory optimized RSMT (MORSMT) construction in order to address the memory overhead for larger nets. Experiments are conducted to evaluate the performance of proposed approach over existing model for varied benchmarks in terms of computation time, memory overhead and wire length. The experimental results showthat the proposed model is scalable and efficient.