Design and implementation of high efficiency square root circuit using Vedic mathematics

The essence of optimizing the VLSI design and improvising their efficiency is the key role in this generation. In this paper, a dedicated design architecture and algorithm is proposed exclusively for finding square root of a number. Finding square root is vital in probabilistic calculation, stochastic problems and communication, quite often iterative architecture is used. This redundant method increases area and power consumption, which also has comparatively higher time for computation. An ancient Vedic sutra, Dvanda yoga, dedicated for finding square root. We effectively used this principle and bestowed it for binary digits. The proposed architecture is compared with existing technique and square root finding circuits. We are using 32bits[16bits+16bits] floating binary input and 16bits[8bits+8bits] binary as output. Implementation is done using Verilog HDL, synthesis by Xilinx 14.5 software for SPARTAN-6. The cost of the algorithm is 360 LUTS, 235 slices and 159 slice flip flop with power consumption of 98.6mW. The proposed design uses shifter, adders and sub-tractor leading to low area and power optimization.