Design and implementation of high efficiency vedic binary multiplier circuit based on squaring circuits

Electronics, and in particular the integrated circuits has been made possible the design of powerful and flexible processors. Having this vision in mind, a dedicated architecture is proposed in this paper which is exclusively used for multiplication of two numbers based on the Vedic sutras. The most significant operation in any signal processing and scientific applications is multiplication. The use of squaring circuits in place of general multipliers can reduce the number of inputs and thereby significantly will reduce the area consumed. To accomplish this, we have implemented Nikhilam Sutra, which is one of the sixteen sutras in Vedic Mathematics. This is dedicated for computing the square of the number. This technique is further extended for finding the product of the binary numbers. The performance for the proposed design is compared with the existing multipliers, on the basis of delay and area utilization. The results prove that the architecture prosed using Nikhilam sutra improves the efficiency considerably. The design has been implemented using Verilog HDL for 8 bit numbers and the synthesis is done using Xilinx ISE 14.5 software.