Synthesis of low power circuits using combined pass logic and CMOS topologies

This paper describes the development of a logic synthesis tool designed specifically to work with a reduced set cell library based primarily on pass logic circuit cells in combination with standard CMOS gates. Circuits synthesized with this tool were compared to circuits synthesized by Synopsys' Design Analyzer using a standard CMOS cell library, for the same benchmarks. An average of 43% improvement in power-delay product has been achieved.