Analysis and Compensation of the System Time Delay in an MMC System

The system time delay (STD) is typically neglected in the design of a modular multilevel converter system. However, the STD can cause different types of deteriorations, including a decrease in system stability, a weakening of the steady-state performance, and a deceleration of the transient response when the load changes. This study first provides the generation mechanism and classification of the system time delay. Then, a linear model is developed to form the basis of the analysis for the system time delay. Subsequently, an analytical method is used to provide an accurate description of the relation between the STD and corresponding deteriorations. Based on the analysis, the optimal design methods of the system controller parameters are proposed to effectively mitigate these deteriorations. Finally, the deteriorations caused by the STD and efficiency of the optimal design methods are demonstrated via experiments.