Analysis and design of energy-efficient data-dependent SRAM

Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technonology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.