Power optimization on MUX mapped circuits

Digital circuits can be represented either by traditional Boolean logic or by BDD (Binary Decision Diagrams). A Multiplexer (MUX) mapped circuit can be obtained after each BDD node is mapped to a 2-input MUX. Some 2-input MUXs can be replaced by 2-input OR/AND/NOR/NAND which usually cause lower power consumption than MUX. In this paper, a set of cell replacement rules is specified. According to these rules we propose an algorithm which converts as many MUXs as possible into ORs and reduces the power of the MUX mapped circuit. MCNC benchmarks are used to test the proposed algorithm. Signal probability and jump density based power calculation model are employed to estimate power consumption. We also use Design Compile (DC) to synthesize the optimized circuit, the results of estimated and synthesized power show the effectiveness of the proposed algorithm.