A clock interpolation structure using DLL for clock distribution in ADC

This paper presents a clock interpolation structure with delay-locked loop (DLL) used for clock generation in high-speed ADCs. By adjusting the sampling clock at the middle-point of the quantizing clock distribution network, the sampling clock and the quantizing clock are aligned. A novel two-path phase/frequency detector (PFD) + charge pump (CP) structure is proposed to ensure the clock-aligning function. A CP with an error operational amplifier is implemented with good current matching characteristic to eliminate the timing error. The design is carried out in 28-nm CMOS technology with a 1.05-V supply. Pre-layout simulation shows that when operating under a 100MHz input clock, the DLL's static phase error is up to 14.3ps while its static power consumption is only 0.1mW.