Computational power analysis of wireless communications systems using operation-level power measurements

This paper presents a novel metric to compare the computational complexity of various digital signal processing (DSP) algorithms used in wireless communications systems. The proposed metric is based on measuring the power consumed by most common mathematical operations, and then, evaluating the total computational power for a given algorithm by considering all mathematical operations performed within that algorithm. Consequently, the widely used computational complexity metric that is computed for each mathematical operation separately is combined into a single metric for the entire algorithm. Therefore, the comparison between different algorithms becomes simpler and more informative. Moreover, the power metric itself is beneficial for practical applications since it can be used to indicate the feasibility of implementing a particular algorithm in field programmable gate array (FPGA) based hardware. The operations considered in this work are addition, subtraction, multiplication and division, all implemented using FPGA for different number of operations and operating frequencies. The obtained results show that the power consumption of such operations is approximately linear as a function of the number of operations and operating frequencies. Moreover, the relative power of the subtraction, multiplication and division with respect to the addition is equal to 1.09, 3.92 and 222.79, respectively. The obtained results are used to evaluate the computational power of several signal processing algorithms in wireless receivers. The obtained results imply that the computational power of several algorithms is prohibitively large for FPGA prototyping.