Reconfigurable cache memory architecture design based on VHDL

In this paper a design of three dimensional reconfigurable cache memory is implemented on FPGA (Field-Programmable Gate Array) using VHDL (Very high speed IC Hardware Description Language). In this design the cache memory architecture allows to change the cache memory size, cache organization and cache block size. Multiple controller units proposed in this design to managing cache memory reconfiguration and to serve in using all allowed cache memory sets for different degrees of associativity and programming the proposed design using hardware description language to evaluate the performance of the design with real hardware components by implemented it on FPGA using Xilinx ISE design suite 13.4. The results show the simulation of the design using (Xilinx ISim simulator).