Standby-power-free integrated circuits using MTJ-based VLSI computing for IoT applications

In the next-generation Internet of Things (IoT) era, it is strongly required to construct new paradigm computer architectures that consume ultra-low power while maintaining high-performance computing. In the distributed wireless sensor network devices working in a harvested energy environment, power-management techniques play important roles to provide the best performance with a limited time-dependent energy source. However, in the present CMOS-only-based VLSI, communication bottlenecks between the memory and logic modules inside a VLSI chip, as well as increasing standby power dissipation and PVT variation effects, limit the solutions to the above problems. In conventional logic-LSI architecture, logic and memory modules are separately implemented, and these modules are connected to each other through global interconnections. Even if the device feature size is scaled down in accordance with the semiconductor technology roadmap [1], the global interconnections are not shortened; rather, they are becoming longer, resulting in longer delay and higher power dissipation due to interconnections. In addition, because on-chip memory modules are “volatile,” they always consume static power to maintain the stored data.