VLSI architecture for IEEE single precision floating point moving average calculator

Moving average is largely used in various image and signal processing applications. Direct calculation of moving average requires a large number of additions which depends upon the segment length. A moving average calculation method which calculates the moving average by updating the previous moving average output with the help of two subtractions regardless the segment length is widely used. This method can be implemented in fixed point arithmetic by using two subtractors and a divider. But, this method cannot be implemented for IEEE floating point arithmetic directly as floating point adder/subtractor have the latency more than one clock cycle. In this paper, a reformed moving average method for implementing it in the IEEE floating point format is proposed. A resource-optimized architecture of the proposed method is also given in the paper. The proposed architecture is synthesized in Xilinx FPGA XC4VLX100 (Virtex 4). It occupies 2785 slices and the maximum operating frequency is found to be 353.107 MHz.