Reconfigurable computing based on universal configurable blocks-a new approach for supporting performance- and realtime-dominated applications

A novel architecture for reconfigurable computing based on a coarse grain FPGA-like architecture is introduced. The basic blocks contain all arithmetical and logical capacities as well as some registers and will be programmable by sequential instruction streams produced by software compiler. Reconfiguration is related to hyper-blocks of instructions. For the composed reconfigurable processors a classification is introduced for describing realtime, multithreading and performance capabilities.