Research and design of add-based length-scalable dual-field modular multiplication-addition-subtraction

Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public (ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular adder and multiplier at both algorithm and structure level, this paper proposes an add-based length-scalable dual-field modular multiplication-addition-subtraction (ALDMAS), with a high resource reuse rate. The proposed ALDMAS with a 3-level pipeline accelerated structure can support dual-field multiplication and addition of any length within 576bits, therefore, it has a strong adaptability. Moreover this architecture, described by Verilog HDL, is integrated in CMOS 65nm technology library, with circuit maximum clock frequency being 487MHz (1.25~3.5 times of the same type of modular multipliers), and the area being 36548 gates (only 0.23~0.4 times of the related work).