A 1.5 V 10-bit 25 MSPS pipelined A/D converter

A 1.5 V 10-bit 25 MSPS pipelined analog-to-digital converter was implemented using 0.25 /spl mu/m CMOS technology. The converter is based on low-voltage two-stage opamps and a current reference generator for low-voltage operation. It also employs a novel dual-mode voltage booster to achieve good low-voltage operation as well as cost reduction. The current reference generator adopts a newly proposed self charge-pumping architecture with ring oscillator that keeps a reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm/sup 2/ (1700 um/spl times/1300 um) and dissipates 45 mW at 25 MHz clock rate with 1.5 V single supply voltage in measurement result. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.44 LSB and /spl plusmn/0.82 LSB, respectively.