A new lower power Viterbi decoder architecture with glitch reduction

This paper presents a new algorithm for a lower power Add-Compare-Select (ACS) architecture and glitch minimization for the Viterbi decoder which can reduce the complexity of the computation using HSPICE. Our experimental results show an average 7% reduction in power with the same latency at a cost of 3% increase in area compared with the ACS unit introduced by Tsui et al. (1999).