Comparator as IP block for dual-slope ADC in integrated circuits

The paper presents a continuous comparison comparator as an IP block. The comparator is developed in a standard semiconductor manufacturing process of 180 nm and can be applied in the design of system-on-a-chip devices, a dual-slope ADC in particular. This ADC can be used in the design of multimeters, digital thermometers, and other devices. The comparator is modeled in Cadence software. The result of the modeling reveals the comparator delay being less than 12 ns under thermal overload and simultaneous power supply voltage slump. Voltage gain does not go below 104.9 dB at the nominal frequency of 1 kHz. Fast response time and resolution of the comparator allow it to be used as an IP block for a dual-slope ADC with the parameters of 11 effective number of bits, conversion frequency of 1 kHz.