An embedded 0.405 /spl mu/m/sup 2/ stacked DRAM technology integrated with high-performance 0.2 /spl mu/m CMOS logic and 6-level metalization

We have developed an embedded stacked DRAM technology that is integrated with 0.2 /spl mu/m CMOS logic and 6 level metalization. DRAM-based fabrication process enables a memory cell size of 0.405 /spl mu/m/sup 2/ with a 0.23 /spl mu/m design rule. This technology will enable a system-on-a-chip (SOC) with more than 100 Mbits of DRAM capacity on a practical chip size.