Microelectronics thin films and boundaries characterized by local electro-thermal measurements

Heat dissipation is one of the main challenges faced by microelectronics due to the increase of integration density. From Silicon-On-Insulator (SOI) technology to 3D-stacked technologies, accurate thermal models are needed to quantify the thermal performances of new devices/packages. Several materials (SiO
₂
, SiN) and thicknesses (from 30 to 540 nm), typically used in the advanced-interconnect levels of microelectronics, are thermally characterized in order to account for heat transport phenomena linked to thermal boundary resistances and ballistic conduction. A mid-term goal is to develop a large library of effective thermal conductivities of materials used in microelectronics. To measure thin-film thermal conductivities, we assess nanometer-scale tip Scanning Thermal Microscopy (SThM), a technique based on atomic force microscopy, where a self-heated electrical resistance is added at the probe apex. To analyze the experimental data, finite-element simulations of the probe-sample interaction are performed in order to reproduce numerically the experiments. SThM technique can be more sensitive to contact conductances than to effective thermal conductivities, even for samples with thin layers of SiN and SiO
₂
. Additional characterization of the tip-sample contact should provide a better estimation of conductivities.