Fast automatic failbit analysis for DRAMs

Technological failures of DRAMs (dynamic random-access memories) show up in different fault patterns in the failbit map. An automatic program has been developed for testing, fault pattern recognition, classification, and determination of fault class distributions on chips and wafers. The analysis system consists of an ADVANTEST T 3332 memory tester and an ADVANSTAR network with a connection to a remotely located mainframe computer. Selected wafers are tested using the same test conditions as in the production test program in order to reproduce the failbit patterns. The fast automatic failbit analysis was first installed for a 1M DRAM and was later updated for 4M DRAM analysis. Results of the analysis are presented and discussed.<
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