A four-bank memory design of optimized semi-parallel polar decoder

Polar code, which is capable of achieving channel capacity, is known as a promising forward error correction (FEC) code in coding theory. In this paper, a four-bank memory architecture is proposed for polar decoder to store the initial and the intermediate processing data. Based on the proposed load-balance data allocation scheme, each memory bank is able to be equipped with only two access ports, while providing enough data bandwidth demand. Besides, the proposed semi-parallel successive cancellation (SC) polar decoder is optimized by employing the efficient p node and the merged computation of f and g nodes to reduce the decoding latency, which can at most get 62.5% speed improvement with enough processing elements (PEs). In addition, the proposed four-bank memory design can reduce the overall size of memory especially with higher level of parallelism.