Highly consistent bulk driven quasi floating gate (BDQFG) PMOS pseudo-resistor design and implementation in 0.18 micron meter technology

A highly linear Bulk Driven Quasi Floating Gate (BDQFG) PMOS pseudo-resistor is proposed using scaled capacitive voltage divider and gate voltage balancing circuitry. The concept of Incremental Resistance and %Consistency has been discussed and compared with already existing topologies in the literature. With the proposed circuit configuration in this paper, we have been able to achieve a resistance of 1TO̅ for swept voltage ranging from -1V to 760mV along with a consistency factor of 90 %. Value of this resistance was found to increase to 3.5TO̅ when the voltage values were swept from 760mV to 880mV and then remained constant till 1V value of swept voltage at zero Volt applicable to bulk of the device (V
_B
= 0V). Incremental Resistance (IR) was found to be getting highly consistent (~ 98 %) at V
_B
= 0.6V over complete range of swept voltage with resistance values almost fixed to 1 TO̅. All the simulations have been conducted using 0.18 micron meter technology 6M1P standard CMOS process using BSIM3V3 PMOS transistor model. Proposed design of circuit is expected to find applications in bio-medical and RF field where there is a dire need to curb noise signals.