Design of high frequency D flip flop circuit for phase detector application

A low power, high frequency positive edge D flip flop circuit is implemented. Its operating frequency is 5GHz with a supply voltage of 1.8 V produces a output at a positive edge triggered signal. It consists of 16 transistor which compel low power of 10.42 μW with a phase noise of −147dBc/Hz and output noise −154.77dB at offset frequency 1 MHz, Circuits is also tested at different corner frequency and has minimal area of 88.571μmm² simulation of results is done by cadence tools in 90nm CMOS process The proposed D flip flop has outplayed the prior research in terms of performance metrics.