Realization of various error mitigation techniques for SRAM based FPGA

SRAM based FPGAs are useful in harsh radiation environments. These type of reconfigurable devices are susceptible to radiation effects which causes faulty outputs, which will lead the system to malfunction or some time system failure. Single Event Upsets(SEUs) are the most general consequence for FPGAs which is based on SRAM, as it might modify the user logic which uses the memory cells as well as memory which is being configured. Different mitigation techniques are realized for SRAM based FPGAs to mitigate SEUs. The general approach to mitigation is redundancy techniques which are based on hardware, software and information redundancy. In this paper, widely used mitigation techniques such as TMR, DWC-CED, RPR, Quadded logic are explained in brief and implemented on Xilinx Spartan 6 FPGA. A thorough comparison of resource utilization by the techniques has been done, applying all the techniques on single design problem. A concluding remark is presented at the end of the paper.