Abstract:
Synergistic processing between multiple instruction set architecture (ISA) cores and heat flows in a 3D heterogeneous multicore chip exacerbates the complexity of thermal...Show MoreNotes: IEEE Xplore Notice to Reader: It is recommended and agreed upon by the authors and the Editor-in-Chief of the IEEE Transactions on Computers that the article "STEM: A Thermal-Constrained Real-Time Scheduling for 3D Heterogeneous- ISA Multicore Processors," by Ting-Hao Tsai, Ya-Shu Chen, Xue-Xin He, and Cheng-Yu Li published in the IEEE Transactions on Computers, vol. 67, no. 6, pp. 874-889 Digital Object Identifier 10.1109/TC.2017.2783941 should not be considered for citation purposes. We regret any inconvenience this may have caused. Paolo Montuschi Editor-in-Chief IEEE Transactions on Computers
Metadata
Abstract:
Synergistic processing between multiple instruction set architecture (ISA) cores and heat flows in a 3D heterogeneous multicore chip exacerbates the complexity of thermal problems. To satisfy performance and temperature requirements, a thermal size ratio detection method is proposed to control the heat generated by task executions with consideration of synergistic processing. At run-time, a Synthetic Thermal-Efficient Manager (STEM) is proposed to dispatch tasks and thermal sizes to cores and to adjust the heat generated in each core through dynamic voltage and frequency scaling. A schedulability test with a degradation factor from synergistic processing is first derived to guarantee that the timing and thermal constraints are met for all tasks in a 3D heterogeneous-ISA multicore processor. Finally, a series of simulations obtain encouraging performance results for the proposed methodology, and a case study using commercially available technology is performed to validate the practicability of the proposed approach.
Notes: IEEE Xplore Notice to Reader: It is recommended and agreed upon by the authors and the Editor-in-Chief of the IEEE Transactions on Computers that the article "STEM: A Thermal-Constrained Real-Time Scheduling for 3D Heterogeneous- ISA Multicore Processors," by Ting-Hao Tsai, Ya-Shu Chen, Xue-Xin He, and Cheng-Yu Li published in the IEEE Transactions on Computers, vol. 67, no. 6, pp. 874-889 Digital Object Identifier 10.1109/TC.2017.2783941 should not be considered for citation purposes. We regret any inconvenience this may have caused. Paolo Montuschi Editor-in-Chief IEEE Transactions on Computers
Published in: IEEE Transactions on Computers ( Volume: 67, Issue: 6, 01 June 2018)