Power efficiency and delay reduction of self gated resonant (SGR) clocked flip flop with H-Tree

The clock distribution network consists of the clocked tree and flip flops. In this paper we have designed sense amplifier energy recovery (SAER), static differential energy recovery (SDER), differential conditional capturing energy recovery (DCCER), signal conditional capturing energy recovery (SCCER) and self gated energy recovery (SGR) flip flops. Among these flip flops SGR flip flop is giving as best power dissipation (61.2nw). In this paper we have also implemented H-Tree which has 16 clock nodes, in this H-Tree Each and every clock node connected with SGR flip flop. We have calculated the power dissipation, setup time, hold time for the implemented H-Tree. This paper is also proposes a 4×4 array multiplier with the help of H-Tree proposed in this paper. This 4×4 array multiplier is implemented in single stage with SGR flip flop, and also we have calculated the power dissipation for a 4×4 array multiplier.