A fast lock-on time mixed mode DLL with 10 ps jitter

We propose a mixed mode Delay Locked Loop (DLL) for low jitter clock recovery and fast lock-on time. A digital FDL (Fixed Delay Line) compensates initial large phase error and an analog VCDL (Voltage Controlled Delay Line) compensates small static phase error to obtain low jitter. The lock-on time of the mixed mode DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz.