Retiming for high speed and low power design

The positioning of flip-flops in a sequential circuit is related to the power dissipation as well as the clock period of the circuit. We show that genetic algorithms can be used to find efficiently the optimal positioning for the power performance of CMOS digital circuits without sacrificing the clock periods. As the result of evaluating our design method, we reduce dissipation of power about 9-10% with preserving optimal clock period.