High performance CMOS dual-modulus prescaler using selective latch technique

This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 /spl mu/m CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.