A bias dependent source/drain resistance model in LDD MOSFET devices for distortion analysis

In order to describe nonlinear distortion behavior precisely, an equivalent resistance model for n/sup -/ source/drain regions of an LDD MOSFET featuring gate bias and drain bias dependence is implemented. Separating the LDD device into an intrinsic MOSFET and two buried channel (BC) MOSFETs, a resistance model has been developed in a physically consistent manner. The proposed resistance model was confirmed using 2D device simulation results and its viability for distortion analysis has been investigated.