Implementation of 4-BIT universal shift register using diode free adiabatic logic

In digital circuits, shift registers are used as the basic memory units. This paper presents a low power adiabatic Universal Shift Register, which can perform both serial and parallel shift operations. Since power dissipation is a critical factor many low power dissipation techniques have been proposed but most of these techniques have some trade-offs. Adiabatic logic technique as compared to that of a conventional CMOS technique shows promising results. A type of adiabatic technique, DFAL (Diode Free Adiabatic Logic), has been studied in this paper and NOR gate, NAND gate, XOR gate, D Flip-Flop and Universal Shift Register have been designed using this configuration. DFAL circuits are analyzed based on transistor count, power dissipation and delay. All the circuits are simulated in Pyxis (Mentor Graphics) 180nm technology at 1.8V.