8-Bit high speed, power efficient SAR ADC designed in 90 nm CMOS technology

In this work a high speed, power efficient successive approximation register (SAR) analog to digital converter (ADC) is designed using 90nm CMOS technology. Double tail dynamic latched comparator is used instead of conventional comparator which shows the significant reduction in power consumption and increases in the device speed. The simulation results indicate the suitability of the proposed novel structure with 3.933Watt power consumption (24.61% Power saving) and 250MHz sampling frequency for replacing the conventional SAR ADC CMOS structure.