Design of CBNS Nibble Size adder using pass transistor logic circuit: Extension to FPGA implementation

This paper focuses on the design of CBNS Nibble Size adder for fast signal processing. A modular based approach has been undertaken both for Pass Transistor as well as Gate Level abstraction. The necessary interconnection between the modules has been done using the structural level design method in Verilog based on conceptual approach for CBNS addition. Simulation, both using ModelSim Altera Starter Edition 6.6d and Xilinx ISE design suite 13.4 confirms the logical verification of the proposed adder. Gate level implementation of the proposed adder on Spartan 3A, XC3S700A FPGA platform reveals 72.8 % reduction in number of LUTs and 51.4 % reduction in path delay over existing CBNS based circuits.