ASIC design of IIR butterworth digital filter for electrocardiogram

In this paper, an Application Specific Integrated Circuit (ASIC) is designed for minimum order IIR Butterworth filter by employing fully parallel architecture with Direct Form I and Direct Form II structure and to represent the co-efficient of filter Canonical Signed Digit is used. The benefits to use this representation are reduction in the computational complexity, hardware requirement which ultimately reduces the area requirement and power consumption. The structures are employed to design this IIR Butterworth low pass filter on Cadence platform. The Verilog language is used for coding purpose for given filter specification. The filter specification such as cut off frequency, sampling frequency is chosen according to Electrocardiogram application i.e 100 Hz and 1 kHz respectively. The main objective of this paper is to give a comparison between Direct Form I structure and Direct Form II structure on the basis of power consumption, area requirement and Speed. Simulation results show that Direct form II structure of filter is 20% faster than Direct Form I.